The invention relates to a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device using a salicide process that reduces the resistance of a gate electrode.
The rapid decrease of the design rule of circuit patterns that of semiconductor devices has resulted in increases in the degree of integration of such devices. Therefore, attempts to realizing a circuit pattern having finer critical dimensions (CDs) has been made. As the CD of the circuit pattern is reduced, the resistance is expected to increase. This increase in the resistance may act as a factor that lowers an operation speed of the semiconductor device.
With the reduction of the design rule, the CD of a gate that constitutes the transistor is also reduced and the resistance of the gate itself rapidly increases. The increase in the resistance of the gate that acts as a word line may act as a factor that lowers operating speed of the transistor. Therefore, efforts to improve gate resistance have been made. Meanwhile, as the CD of the gate is reduced, a short channel effect due to reduction in the channel width results. In order to improve this short channel effect, a junction impurity region is formed more shallowly. Therefore, a surface resistance in the junction is increased and thus the operation speed is also lowered.
In order to increase the device operation speed of the transistor, development of a method capable of improving the gate resistance or the surface resistance of the junction is required.